{"id":194,"date":"2025-01-13T20:40:14","date_gmt":"2025-01-13T20:40:14","guid":{"rendered":"https:\/\/research.ece.ncsu.edu\/ascends\/?page_id=194"},"modified":"2025-01-13T20:47:52","modified_gmt":"2025-01-13T20:47:52","slug":"key-contribution","status":"publish","type":"page","link":"https:\/\/research.ece.ncsu.edu\/ascends\/key-contribution\/","title":{"rendered":"Key Contribution"},"content":{"rendered":"\n

Integration<\/strong>:<\/p>\n\n\n\n

V. Misra, S. Venkatesan, C. Hobbs, B. Smith, J. Cope and E. Wilson,\u00a0\u00a0\u201cMethod for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions<\/em>\u201d Patent # 5,960,270, Issue Date Sept 1999.<\/p>\n\n\n\n

\u2022Citations 279<\/p>\n\n\n\n

1.This patent demonstrated a novel method to form a self-aligned reverse gate MOSFET flow (also known as gate-last). This patent is a key contribution to the field especially given that Intel has announced a gate-last process.<\/p>\n\n\n\n

2.This patent has been cited by major semiconductor companies including Intel, Micron, IBM, Applied Materials, ST Microelectronics, AMD (now Global Foundries), etc.<\/p>\n\n\n\n

3.Dr. Misra was the lead inventor and provided the primary integration concept of a sacrificial gate.\u00a0<\/p>\n\n\n\n

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Interface Layer<\/strong><\/p>\n\n\n\n

RPECVD Si3N4\u00a0gatestacks\u00a0with polysilicon gate electrodes were formed\u00a0in situ\u00a0<\/p>\n\n\n\n

\u2022Mobility values for NMOS transistors showed reduced peak values. PMOS devices showed nonexistent inversion characteristics and mobility values. <\/p>\n\n\n\n

\u2022High density of donor type states near the valence band which shifts the flatband values and reduces the involvement of hole carriers in the creating the inversion layer. <\/p>\n\n\n\n

\u2022Finally, if a 6 \u00c5 SiO2 layer was inserted between the silicon and the Si3N4 layer, full recover of the mobility was observed for both NMOS and PMOS devices. <\/p>\n\n\n\n

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Work Function extraction<\/strong><\/p>\n\n\n\n

\u2022R. Jha, J. Gurganos, Y.H. Kim, R. Choi, J. Lee and V. Misra \u201cA Capacitance Based Methodology for Work Function Extraction of Metals on High-K Dielectrics<\/em>\u201d, June, IEEE EDL, 25(6), pp. 420-423, 2004. (Citations: 137<\/strong>). <\/p>\n\n\n\n

\u2022This was the first paper to present a robust approach for measuring the work function of metal electrodes by independently varying the bottom and top dielectric thicknesses. This approach extracted the effective work function which is a combination of interface reactions, dipoles or Fermi level pinning. <\/p>\n\n\n\n

High K\/metal Gates<\/strong>:<\/p>\n\n\n\n

\u2022V. Misra, H. Zhong and H. Lazar, \u201cElectrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS<\/em>\u201d, IEEE Electron Device Letters, vol 23, 6, 2002. (Scopus Citations: 115<\/strong>). This paper was one of the first to demonstrate the feasibility of using binary metal alloys in MOSFETs by showing minimal mobility degradation under gate first MOSFET flow.  Misraled this work with her graduate students Zhong and Lazar).  <\/p>\n\n\n\n

\u2022<\/p>\n\n\n\n

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High K interfaces:<\/strong><\/p>\n\n\n\n

\u2022V. Misra, G.P. Heuss, H. Zhong, \u201cThe use of MOS Capacitors to Detect Interactions of Hf and Zr gate with SiO<\/em>2<\/sub><\/em>, APL, 78(26), pp. 4166-8, Jun. 2001. (Scopus citations: 42<\/strong>).<\/p>\n\n\n\n

\u2022This was one of the first papers to discuss the instability of low work function gates such as Hf and Zr and their high reactivity towards the underlying dielectric. The paper used MOS structures to understand the fundamental nature of reactivity. Misra led this work with her students: Zhong and Heuss)<\/p>\n\n\n\n

\u2022V. Misra, G. Lucovsky and G. Parsons, \u201cIssues in high-K gate stack interfaces<\/em>\u201d, MRS Bulletin Issue, 27(3), pp. 212-216, Mar. 2002 (Scopus Citations: 41<\/strong>). <\/p>\n\n\n\n

\u2022This was one of the first review papers in the field of metal gatestacks that addressed the fundamental understanding of bonding and electronic structure at the high-K and metal gate interface. In this joint paper, Misra led the electrode-interface discussion).<\/p>\n\n\n\n

\u2022H. Zhong, G.P. Heuss and V. Misra, \u201cCharacterization of RuO<\/em>2<\/sub><\/em> Electrodes on ZrSiO<\/em>4<\/sub><\/em> and ZrO<\/em>2<\/sub><\/em> Dielectrics for Si-PMOSFETs<\/em>\u201d, APL, 78(8), pp.1134-6, Feb. 2001. (Scopus Citations: 46<\/strong>). <\/p>\n\n\n\n

\u2022This was one of the first papers to discuss differences between NMOS and PMOS electrodes with respect to their stability on high-K dielectrics. Both Zhong and Heuss were Misra\u2019s graduate students who led the work).<\/p>\n\n\n\n

Metal Gates<\/strong>:<\/p>\n\n\n\n

\u2022H. Zhong, G.P. Heuss and V. Misra, \u201cElectrical Properties of RuO<\/em>2<\/sub><\/em> gates for Dual Gate CMOS<\/em>,\u201d IEEE EDL, 21(12) pp. 593-5, Dec. 2000. (Scopus Citations: 47<\/em>). <\/p>\n\n\n\n

\u2022This was the first paper to evaluate the properties of a metal oxide as a gate electrode. Many groups have since continued the evaluation of metal oxides as gate candidates. Zhong and Heuss were graduate students of Prof. Misra who led the work).<\/p>\n\n\n\n

\u2022H. Zhong, H. Zhong, S.H. Hong, Y. S. Suh, G. Heuss and V. Misra, \u201cProperties of Ru-Ta Alloys as Gate Electrodes for NMOS and PMOS Silicon Devices,<\/em>\u201d IEEE IEDM Technical Digest, pp. 467-70, 2001. (Scopus Citations: 24<\/em>). <\/p>\n\n\n\n

\u2022This was one of the first papers to demonstrate that binary metal alloys can tune work function from NMOS to PMOS while also producing thermally stable films due to intermetallic bonding. This work also produced a patent.[ 6,873,020]  Zhong (now at AMD), Suh (Spansion) and Heuss (Intel) were students of Dr. Misra who led the work. Hong was a post-doc.) <\/p>\n\n\n\n

\u2022B. Chen, R. Jha and V. Misra, \u201cWork function tuning via interface dipole by ultrathin reaction layers using AlTa and AlTaN alloys\u201d, IEEE EDL 27(9): 731-733, Sept 2006. <\/p>\n\n\n\n

\u2022(This paper proposed a novel methodology to use a dipole (Al-O-Ta) between the dielectric and metal electrode to gain large shifts in PMOS threshold voltage. This approach is advantageous since the location is removed from the bottom interface. Both Chen and Jha were graduate students of Prof. Misra who led the work.) <\/p>\n\n\n\n

\u2022J.H. Lee, H. Zhong, Y.S. Suh, G. Heuss, J. Gurganus, B. Chen and V. Misra, \u201cTunable Work Function Dual Metal Gate Technology for Bulk and Non-Bulk CMOS<\/em>\u201d, IEEE IEDM Technical Digest, pp. 359- 362, 2002. (SCI Citations: 38<\/em>). <\/p>\n\n\n\n

\u2022This work demonstrated a novel metal gate process using ultra thin metal bilayer stacks to tune the work function values and result in ease of integration for thermally stable dual metal gates. All authors were graduate students of Dr. Misra who led the work). <\/p>\n\n\n\n

\u2022Y-S. Suh, G. Heuss, J.H. Lee and V. Misra, \u201cEffect of Composition on the Electrical Properties of <\/em>TaSiN<\/em> Metal Gate Electrodes<\/em>\u201d, IEEE EDL,24 (7), pp. 439-441, 2003. (SCI Citations: 22<\/em>). <\/p>\n\n\n\n

\u2022This work demonstrated that the work function critically depends on composition and a carefully controlled TaSiN layer provided both a low work function metal and excellent thermal stability. All authors were graduate students of Prof. Misra who led the work.)<\/p>\n\n\n\n

\u2022Y-S. Suh, G.P. Heuss and V. Misra, \u201cElectrical<\/em> characteristics of <\/em>TaSi<\/em>x<\/sub><\/em>N<\/em>y<\/sub><\/em>\/SiO<\/em>2<\/sub><\/em>\/Si structures by Fowler-<\/em>Nordheim<\/em> current analysis\u201d<\/em>, APL 80 (8) pp. 1403-5, 2002. (SCI Citations: 25<\/em>. <\/p>\n\n\n\n

\u2022This paper was a follow on to our initial 2001 VLSI paper, which was the first to demonstrate the use of TaSiN as a highly robust and thermally stable gate electrode. Many groups have since evaluated TaSiN in CMOS devices. Both authors were graduate students of Prof. Misra who led the work.)<\/p>\n\n\n\n

Hybrid Molecular Devices (Lindsey Chem)<\/strong><\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n
\"\"<\/figure>\n\n\n\n

Gate Stacks for GaN:<\/strong><\/p>\n\n\n\n

\"\"<\/figure>\n","protected":false},"excerpt":{"rendered":"

Integration: V. Misra, S. Venkatesan, C. Hobbs, B. Smith, J. Cope and E. Wilson,\u00a0\u00a0\u201cMethod for forming an MOS transistor having a metallic gate electrode that…<\/p>\n","protected":false},"author":145,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"page-fullwidth.php","meta":{"footnotes":""},"class_list":["post-194","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/research.ece.ncsu.edu\/ascends\/wp-json\/wp\/v2\/pages\/194","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/research.ece.ncsu.edu\/ascends\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/research.ece.ncsu.edu\/ascends\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/research.ece.ncsu.edu\/ascends\/wp-json\/wp\/v2\/users\/145"}],"replies":[{"embeddable":true,"href":"https:\/\/research.ece.ncsu.edu\/ascends\/wp-json\/wp\/v2\/comments?post=194"}],"version-history":[{"count":2,"href":"https:\/\/research.ece.ncsu.edu\/ascends\/wp-json\/wp\/v2\/pages\/194\/revisions"}],"predecessor-version":[{"id":206,"href":"https:\/\/research.ece.ncsu.edu\/ascends\/wp-json\/wp\/v2\/pages\/194\/revisions\/206"}],"wp:attachment":[{"href":"https:\/\/research.ece.ncsu.edu\/ascends\/wp-json\/wp\/v2\/media?parent=194"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}